1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly to an output circuit of a semiconductor circuit.
2. Description of the Related Art
An output circuit of a semiconductor circuit in which a plurality of semiconductor devices are arranged, is known in Japanese Patent No. 2,646,786 as shown in FIG. 1. In the output circuit, an N-channel MOS transistor is generally used as an output transistor. The on and off states of the output transistor is controlled by a gate driving circuit. A conventional example of the circuit structure of the gate driving circuit is shown in FIG. 2.
A conventional semiconductor output circuit shown in FIG. 1 is comprised of an output transistor 101, a gate driving circuit 102 which supplies a gate signal to the gate of the output transistor 101, a control circuit 103, and a switch 104 connected the source and gate of the output transistor 101. The control circuit 103 has a protection circuit such as an over-current detecting circuit and an over-temperature detecting circuit and transfers a control signal to the gate driving circuit 102.
Referring to FIG. 2, the gate driving circuit 102 is comprised of first and second inverter circuits and a boosting circuit. The first inverter circuit is comprised of a P-channel transistor 122 and an N-channel transistor 123 connected in series. The second inverter circuit is comprised of a P-channel transistor 105, an N-channel transistor 121 of a diode connection, and an N-channel transistor 106. The boosting circuit is comprised of an N-channel transistor 113, a capacitor C and an N-channel transistor 114.
The switch 104 is shown in FIG. 3, and is comprised of an N-channel transistor 131, a resistance R101 and an N-channel transistor 132.
FIG. 4 shows a modification of the semiconductor output circuit in which the gate driving circuit 102 shown in FIG. 2 and the switch 104 shown in FIG. 3 are applied to the circuit shown in FIG. 1. Referring to FIG. 4, in the above conventional semiconductor output circuit, when an output transistor on control signal 108 to turn on the output transistor 101 is supplied to the control circuit 103, a low level is given to the input of the CMOS inverter of the transistors 105 and 106. In the CMOS inverter, the transistor 105 can be turned on quickly. Through the turning on operation of the CMOS inverter, the output transistor 101 is set to the on state. When the gate driving circuit 102 increases the gate voltage of the output transistor 101 higher than the power supply voltage, the transistor 121 with a diode connection is inversely biased to prevent that the charge flows through the P-channel transistor 105. Such prevention enables the gate potential of the output transistor 101 to be kept sufficiently high.
When an output transistor off control signal 109 to turn off the output transistor 101 is supplied to the gate driving circuit 102, the gate voltage of the output transistor 101 becomes the ground potential (0V), and the output transistor 101 is set to the off state. At this time, the N-channel transistor 132 is turned on in response to the output transistor off control signal 109. As a result, the gate and source of the output transistor 101 are connected to form a short circuit, and it is prevented that the output transistor 101 is turned on when the source potential becomes negative.
In such a conventional semiconductor output circuit, the circuit current flows through the gate driving circuit 102 and the control circuit 103, even when the output transistor 101 is in the off state. Thus, dark current at the off time becomes large and the power is wastefully consumed. Moreover, as shown in FIG. 4, when the output transistor 101 is in the off state and when a negative voltage is applied to an output signal line 110, there are parasitic current flow routes. One parasitic current flow route is of the power supply line 111xe2x86x92the transistor 106xe2x86x92the N-channel transistor 132xe2x86x92the output signal line 110, and another parasitic current flow route is of the power supply line 112xe2x86x92the transistor 113xe2x86x92transistor 114xe2x86x92the N-channel transistor 107xe2x86x92the output signal line 110. Therefore, the parasitic current in the switching operation of the switch 104 flows wastefully.
It is demanded to prevent the wasteful consumption current which flows through a control circuit and a switching circuit in the off state of the output transistor and the switching operation.
In conjunction with the above description, a gate driving circuit is disclosed in Japanese Examined Patent Application (JP-B-Heisei 6-81025). In the gate driving circuit, the gate of an output transistor of an N-channel MOS transistor is driven which is used as a source output. A voltage boosting circuit carries out a boosting operating of a voltage according to a trigger inputted and gives a boosted voltage to the gate of the output transistor. A first CMOS inverter circuit inputs a low level signal at the same timing as the trigger inputting and an output point is connected with the gate of the said the output transistor. An N-channel MOS transistor for countercurrent prevention is connected to a point between a P-channel MOS transistor of the first CMOS inverter circuit and the output point of the first CMOS inverter circuit, and the gate and drain thereof are connected to those of the P-channel MOS transistor. A second CMOS inverter circuit is provided in parallel to the first CMOS inverter circuit, and an input point is same as that of the first CMOS inverter circuit, and an output point is connected with a background gate of the N-channel MOS transistor for the countercurrent prevention.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent application (JP-P2000-58671A). In this reference, a level shift circuit is composed of an N-channel MOSFETs and a P-channel MOSFETs. The N-channel MOSFETs are used for the high side and low side of an output stage circuit. A resistance and a diode are provided in parallel to the N-channel MOSFET on the said high side between the gate and source. The cathode of the diode is connected with the gate and the anode of the diode is connected with the source.
Therefore, an object of the present invention is to provide an output circuit of a semiconductor circuit, in which it is possible to prevent wasteful consumption current.
Another object of the present invention is to provide an output circuit of a semiconductor circuit, in which it is possible not to flow a parasitic current when a negative voltage is applied to the source of an output transistor.
In an aspect of the present invention, an output circuit of a semiconductor circuit includes a higher potential side power supply line, a output line on which an output signal is outputted, a control signal line on which a control signal is transferred, a gate signal line on which a gate signal is transferred, an output transistor, a first switch and a gate driving circuit. The output transistor is connected between the higher potential side power supply line and the output signal line to operate in response to the gate signal on the gate signal line. The first switch is connected to the higher potential side power supply line to turn off in response to the control signal of a first state and turn on in response to the control signal of a second state. The gate driving circuit is connected between the first switch and the control signal line to generate the gate signal onto the gate signal line based on a gate control signal when the first switch is turned on.
Here, the output transistor may be a first N-channel transistor. The output circuit may further include a second switch connected between the gate signal line and the output signal line to turn on in response to the control signal of the first state and to turn off in response to the control signal of the second state. In this case, the output circuit may further include a first resistance connected between the gate signal line and the output signal line.
The first switch may include a first P-channel transistor. The control signal is supplied directly to a gate of the first P-channel transistor.
Also, the output circuit may further include second and third resistances connected between the higher potential side power supply line and the control signal line in series. The first switch may include a first P-channel transistor, and the control signal is supplied to a gate of the first P-channel transistor via the third resistance.
Also, the output circuit may further include a protection circuit connected between the higher potential side power supply line and the control signal line to generate the gate control signal from the control signal. The output circuit may further include a lower potential side power supply line, and a protection circuit connected between said higher potential side power supply line and said lower potential side power supply line to generate said gate control signal from said output signal in addition to said control signal. The protection circuit may include at least one of an over-current detecting circuit or an over-temperature detecting circuit, and generates the gate control signal from an output of the at least one of an over-current detecting circuit or an over-heating detecting circuit, in addition to at lease one of the control signal and the output signal.
Also, the output circuit may further include a lower potential side power supply line, and a third switch connected between the higher potential side power supply line and the lower potential side power supply line to generate the control signal of the first state based on a supplied control signal of the second state and to generate the control signal of the second state based on the supplied control signal of the first state and outputs the control signal onto the control signal line. The third switch may connect the control signal line to the lower potential side power supply line in response to the supplied control signal of the first state. In this case, the output circuit may further include a fourth switch and a fifth switch. The fourth switch is connected between the gate signal line and the lower potential side power supply line to generate a switching control signal of the first state in response to the supplied control signal of the second state and to generate the switching control signal of the second state in response to the supplied control signal of the first state. The fifth switch is connected between the gate signal line and the output signal line to turn on in response to the switching control signal of the first state and to turn off in response to the switching control signal of the second state.
Also, the fourth switch may include a fourth resistance connected with the gate signal line, and a second N-channel transistor. The second N-channel transistor is connected between the fourth resistance and the lower potential side power supply line to turn off in response to the supplied control signal of the second state and to turn on in response to the supplied control signal of the first state. In this case, it is desirable that the fourth resistance has a resistance value for suppressing parasitic current.
The third switch may include a fifth resistance connected with the higher potential side power supply line, and a third N-channel transistor connected between the fifth resistance and the lower potential side power supply line to receive the supplied control signal at a gate of the N-channel transistor. The control signal line is connected to a node between the fifth resistance and the third n-channel transistor.
Also, the third switch may include a fifth resistance connected with the higher potential side power supply line, sixth and seventh resistances connected with the lower potential side power supply line in series, and a third N-channel transistor connected between the fifth resistance and the lower potential side power supply line to receive the supplied control signal at a gate of the third N-channel transistor via the sixth resistance. The control signal line is connected to a node between the fifth resistance and the third n-channel transistor.
Also, the third switch may include a second P-channel transistor connected with the higher potential side power supply line, and a fourth N-channel transistor connected between the second p-channel transistor and the lower potential side power supply line. The supplied control signal is supplied to a gate of each of the fourth N-channel transistor and the second P-channel transistor, and the control signal line is connected to a node between the fourth N-channel transistor and the second P-channel transistor.